PLCverif — Verification report

Verification stages

Phase	Result	Runtime
Parsing source code	Successful	0 ms
Control-flow declaration generation	Successful	66 ms
Requirement representation	Successful	27 ms
Reductions (CFD)	Successful	42 ms
Model preparation	Successful	11 ms
Reductions (CFI)	Successful	33 ms
NuSMV model building	Successful	1 ms
NuSMV execution	Successful	1312 ms
NuSMV output parsing	Successful	8 ms
Result diagnosis	Successful	0 ms
Reporting	Unknown

Log

Message

Severity

Stage

Verification tool outputs

STDERR

STDOUT

*** This is NuSMV 2.6.0 (compiled on Wed Oct 14 15:37:51 2015)
*** Enabled addons are: compass
*** For more information on NuSMV see <http://nusmv.fbk.eu>
*** or email to <nusmv-users@list.fbk.eu>.
*** Please report bugs to <Please report bugs to <nusmv-users@fbk.eu>>

*** Copyright (c) 2010-2014, Fondazione Bruno Kessler

*** This version of NuSMV is linked to the CUDD library version 2.4.1
*** Copyright (c) 1995-2004, Regents of the University of Colorado

*** This version of NuSMV is linked to the MiniSat SAT solver.
*** See http://minisat.se/MiniSat.html
*** Copyright (c) 2003-2006, Niklas Een, Niklas Sorensson
*** Copyright (c) 2007-2010, Niklas Sorensson

Output to file: C:\Users\andia\AppData\Local\Temp\PLCverif-output2134765264300002137\case40.smv.cex


Plug-in key-value store

• nusmv$expression_type = Ctl

Effective settings used for the verification

-description = ""
-id = case40
-job = verif
-job.backend = nusmv
-job.backend.algorithm = Classic
-job.backend.binary_path = C:\Users\andia\Egyetem\nusmv\bin\NuSMV.exe
-job.backend.df = true
-job.backend.dynamic = true
-job.backend.locref_req_strategy = false
-job.backend.req_as_invar = false
-job.backend.timeout = 5
-job.reporters.0 = html
-job.reporters.0.hide_internal_variables = true
-job.reporters.0.include_settings = true
-job.reporters.0.include_stack_trace = false
-job.reporters.0.min_log_level = Warning
-job.reporters.0.show_logitem_timestapms = false
-job.reporters.0.show_verification_console_output = true
-job.reporters.0.use_lf_value_representation = false
-job.reporters.1 = summary
-job.req = pattern
-job.req.inputs.0 = instance.DemandAvailability
-job.req.inputs.1 = instance.AvailabilityChanged
-job.req.inputs.2 = instance.ComponentSetup_Done
-job.req.inputs.3 = instance.CommandIn
-job.req.inputs.4 = instance.Unit_is_Type1
-job.req.inputs.5 = instance.Sig1_from_Type2
-job.req.inputs.6 = instance.Sig2_from_Type2
-job.req.inputs.7 = instance.Orientation_Valid
-job.req.lowerBounds.value.0 = BYTE#251
-job.req.lowerBounds.variable.0 = instance.CommandIn
-job.req.pattern_id = pattern-invariant
-job.req.pattern_params.1 = instance.outputs_match
-job.req.upperBounds.value.0 = BYTE#255
-job.req.upperBounds.variable.0 = instance.CommandIn
-lf = step7
-lf.compiler = Step7v55
-lf.entry = aggr_40
-name = ""
-output = C:\Users\andia\AppData\Local\Temp\PLCverif-output2134765264300002137
-reductions.0 = basic_reductions
-reductions.0.ExpressionPropagation_maxage = 50
-reductions.0.ExpressionPropagation_maxexprsize = 100
-reductions.0.ExpressionPropagation_maxlocations = 50000
-reductions.0.fine_logging = false
-reductions.0.print_vardep_graph = false
-reductions.0.show_progress = false
-sourcefiles.0 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\test.scl
-sourcefiles.1 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\example_10.scl
-sourcefiles.2 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\common.scl
-sourcefiles.3 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\example.scl
-sourcefiles.4 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\example_14.scl
-sourcefiles.5 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\example_40.scl
-sourcefiles.6 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\example_12.scl
-sourcefiles.7 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\example_36.scl
-sourcefiles.8 = C:\Users\andia\Egyetem\student-serban-bsc\tdk-latex\src\appendix\examples\PLCverif\example_34.scl